The present invention relates to DRAM circuits and, more specifically, to a circuit and method for maintaining a desired read latency in a high speed DRAM.
A typical DRAM memory system has an external DRAM controller that makes read and write requests to a DRAM memory device. When making a read request, the controller expects data within the memory device to be available on a data bus within a predetermined read latency, which is usually a predetermined number of system clock cycles, which are external to the DRAM device, after a read request is made by the controller e.g., eight external clock cycles.
Problems with maintaining read data latency in high speed DRAM arise from the necessity to align data with the external clock using an internal delay locked loop (DLL), which generates timing signals, including a read clock signal, for internal DRAM operations. The phase relationship between the external clock, an internal command/address capture clock and the DLL output clock, which is used to generate the read clock signal, is completely arbitrary and dependent on frequency and process, voltage, and temperature (PVT) variations. The command capture clock is delayed relative to the external clock by the clock receiver and other clock distribution delays. The DLL is back timed relative to the external clock by the delay of the data output circuits, but receives its input from an internal clock receiver and also has adjustments made to its output signals that are not synchronized with the external clock. A difference in phase near or greater than a complete clock cycle creates difficulty in controlling timing between the command/address capture clock domain and the DLL clock domain.
Internally the DRAM memory device has its own DLL driven clock system that receives the external clock signal and develops from the external clock several different internal clock signals, including a read clock signal, for internal operation of the memory device. The internal clock system of known, high speed memory devices produces at least two clock domains. The first clock domain represents the timing used in the bulk of the logic circuits and to drive the memory array. The timing for the first domain is produced from the internal clock receiver, which is buffered from the external free running system clock. The phase of the clock signal in the first domain relative to the external clock is dependent upon delays in the clock receiver that receives the external clock signal. The second domain, also derived from the external system clock, represents the timing of a back-timed read clock signal. This clock domain is produced by the delay locked loop DLL and associated clock trees. This second clock domain produces a read clock for operating data read latches. The read clock is provided to the read latch with a desired phase relationship relative to the external system clock. The second clock domain compensates for delays in the data output path to produce a read clock signal that operates the output data latches to achieve a specified phase alignment with the external system clock.
Neither of these two clock domains accurately reflects the timing of the external system clock, particularly at high frequencies of operation. The timing of the clock signals in the two domains may crisscross one another during memory device operation due to process, voltage and temperature (PVT) variations. Consequently, a problem may arise in that the clock domain responsible for delivery of read data to an output latch may cause this data to be delivered at a different time from when the back-timed read clock for latching that data is present at the latch, or when the data is actually required to be driven to an external bus.
To meet a specified read latency the memory device must be able to count clock signals following receipt of a READ command and activate the output latch and data driver to latch output data with the back-timed read clock and drive the bus at the precise time necessary to produce the specified read latency.
Because the amount of read clock back-timing relative to the data availability becomes indeterminate during high speed operation, it is very difficult to control the read clock and guarantee a correct data output and a specific read latency as measured in external clock cycles.
One solution to these problems is disclosed in U.S. patent application Ser. No. 10/389,807 entitled Method and Apparatus for Establishing and Maintaining Desired Read Latency in High-Speed DRAM which is assigned to the same assignee as the present invention. That document discloses a method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts a first counter, which counts external clock cycles, and is also passed through a slave delay line of a delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock.
Another solution to these problems is disclosed in U.S. Pat. No. 6,687,185 which discloses an apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to control the output of read data by the read clock signal.